Inside Architect Labs’ Two-Week Chip Design

What it means for hiring

Set aside the founders' ages and the two weeks, and the claim worth testing is narrower. Architect Labs says its platform handles around ninety percent of verification without a commercial simulator, then hands over to conventional EDA for sign-off, and that its Redwood test chip came back from a TSMC shuttle working on the first spin. Two weeks was the FPGA prototype. Working A0 silicon is the part that deserves attention, because first-pass silicon is where most chip schedules die.

The company's own line is the hiring story: fewer engineers per project, and more projects. If that holds, the verification engineer who writes testbenches all day is the role under pressure, and the scarce people move to either end of the flow. At the front, architects who can specify a chip precisely enough for a tool to build it. At the back, sign-off, DFT and post-silicon bring-up engineers who decide whether what came out of the fab is the chip anybody asked for. More tape-outs means more bring-up, and bring-up has never been automated. A client planning a custom ASIC programme should put its headcount at the ends, not in the middle.

Read the original at EE Times .