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Marvell is using ECOC in Málaga to show a set of 2nm optical interconnect chips for AI data centres. They include a 400G per lane PAM4 implementation aimed at 3.2T links, an 800G ZR/ZR+ pluggable built on its 2nm Libra coherent DSP with MACsec encryption, 1.6T ZR and coherent-lite O-band technology for links inside and between sites, and a 102.4 Tbps co-packaged optics platform using 200G per lane silicon photonics. The company is running 38 demonstrations at the show, covering 224G SerDes, 1.6T optics and optical memory fabrics.

Marvell went from 5nm to 3nm to 2nm optical DSPs in three product generations, and each step pushes more of the design problem into the analogue and optical front end. At 400G per lane the hard part is the signal integrity between the DSP, the driver, the modulator and the fibre, not the digital logic. That needs high-speed analogue and mixed-signal designers, silicon photonics and packaging engineers, and test engineers who can characterise links at these rates. Co-packaged optics moves the optics onto the accelerator package, so switch and GPU teams now need photonics people too. Europe has strong photonics clusters in Eindhoven, Berlin and Scotland, and module makers and hyperscalers will look there first.

Read the original at eeNews Europe .

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